Engineering 238

Digital Logic Design

 Engineering 238 Schedule

Last page update 1/18/10

(version 0.98)  Keep looking here for updates and changes...  
 
Week # Tuesday Thursday Labs
1:
Jan 11-15
  		Introduction
Number Representations
Conversions
1.1,1.2,1.3

Negative Numbers, Arithmetic, Codes, Error Detection, Hardware 

1.4,1.5,1.7,1.8

Introduction to Equipment 

Logic Gate Verification
2:
Jan 18-22 		Switching Algebra and Logic Gates
1.7,1.8,2.1,2.2,2.3
 Logic Gates
AND, OR, ETC., Minterm and Maxterms
2.3,2.4
 Basic Two Level Circuits
Logic Analyzer
3:
Jan 25-29 		Representation and Implementation of Logic Functions
(Census date 9/12/06)
 Minimal realizations
Karnaugh Maps
3.1-3.5 		One Gate Implementation - NAND Circuits
4.1,4.2,4.3
4:
Feb 1-5 		Don't cares
3.3
practice test handout
 Test 1 Circuit Reductions and Multiple Outputs.
5:
Feb 8-12 		Timing Diagrams
Gremlins
3.6
 Combinational Logic Design Multiplexors
4.6,4.7
 Timing Circuits
6:
Feb 15-19 		Decoders
4.7		 Adders, Subtractors
6.5,6.6 		Multiplexors/ Demultiplexors
7:
Feb 22-26 		 ROMs, PLAs.
4.8,4.9 		Test 2 Adders - Ripple and look ahead carry. 6.7
8:
Mar 1-5 		Hardware Description Languages 5.1-5.10
mid-term grades due 		VHDL Continue with adder lab
XX:
Mar 8-12 		Break Break Break
9:
Mar 15-19 		Intro to SR latches
Sequential Components
Flip-flops 		 JK latches and flip flops VHDL
Continue with adder lab
10:
Mar 22-26 		Flip Flops State Diagrams
Implementation 		Flip Flops and Counter
11:
Mar 29-Apr 2 		Review Test 3 States/Bono Counter
12:
Apr 5-9 		Synchronous Sequential Machines
Traffic Light
 Sequence detectors
State Reduction
Last day to drop with a "W. " 		State Sequences
13:
Apr 12-16 		Mealy and Moore
Review
 Registers
Universal Shift Registers 		Registers
14:
Apr 19-23 		Asynchronous Sequential Machines Circuit Examples Computer Organization Soundtraxx
Final:
Apr 26-30 		Final Exam (Test 4)
2:15 Thursday
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######   Break!   ######
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